/*
 * Copyright (c) 2022, IMMORTA Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * - Redistributions of source code must retain the above copyright notice, this list
 *   of conditions and the following disclaimer.
 *
 * - Redistributions in binary form must reproduce the above copyright notice, this
 *   list of conditions and the following disclaimer in the documentation and/or
 *   other materials provided with the distribution.
 *
 * - Neither the name of IMMORTA Inc. nor the names of its
 *   contributors may be used to endorse or promote products derived from this
 *   software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef SPI_REG_ACCESS_H
#define SPI_REG_ACCESS_H

/*!
 * @file timer_reg_access.h
 * @brief This file declares or defines timer register access functions
 */

/*******Includes***************************************************************/
#include "device_registers.h"
#include "spi_drv.h"

/*******Definitions************************************************************/
/* Configuration Register Bit Fields */
#define SPI_CFGR_FRAMESZ(x)    (((uint32_t)(((uint32_t)(x)) << SPI_CFGR_FRAMESZ_Pos)) & SPI_CFGR_FRAMESZ_Msk)
#define SPI_CFGR_SPIEN(x)      (((uint32_t)(((uint32_t)(x)) << SPI_CFGR_SPIEN_Pos)) & SPI_CFGR_SPIEN_Msk)
#define SPI_CFGR_TMSBF(x)      (((uint32_t)(((uint32_t)(x)) << SPI_CFGR_TMSBF_Pos)) & SPI_CFGR_TMSBF_Msk)
#define SPI_CFGR_RMSBF(x)      (((uint32_t)(((uint32_t)(x)) << SPI_CFGR_RMSBF_Pos)) & SPI_CFGR_RMSBF_Msk)
#define SPI_CFGR_CPOL(x)       (((uint32_t)(((uint32_t)(x)) << SPI_CFGR_CPOL_Pos)) & SPI_CFGR_CPOL_Msk)
#define SPI_CFGR_CPHA(x)       (((uint32_t)(((uint32_t)(x)) << SPI_CFGR_CPHA_Pos)) & SPI_CFGR_CPHA_Msk)
#define SPI_CFGR_TDMAEN(x)     (((uint32_t)(((uint32_t)(x)) << SPI_CFGR_TDMAEN_Pos)) & SPI_CFGR_TDMAEN_Msk)
#define SPI_CFGR_RDMAEN(x)     (((uint32_t)(((uint32_t)(x)) << SPI_CFGR_RDMAEN_Pos)) & SPI_CFGR_RDMAEN_Msk)
#define SPI_CFGR_MASTER(x)     (((uint32_t)(((uint32_t)(x)) << SPI_CFGR_MASTER_Pos)) & SPI_CFGR_MASTER_Msk)
#define SPI_CFGR_CSPOL(x)      (((uint32_t)(((uint32_t)(x)) << SPI_CFGR_CSPOL_Pos)) & SPI_CFGR_CSPOL_Msk)
#define SPI_CFGR_PINCFG(x)     (((uint32_t)(((uint32_t)(x)) << SPI_CFGR_PINCFG_Pos)) & SPI_CFGR_PINCFG_Msk)

/* Chip Select Configuration Register Bit Fields */
#define SPI_CSCFGR_SETUP(x)    (((uint32_t)(((uint32_t)(x)) << SPI_CSCFGR_CSSETUP_Pos)) & SPI_CSCFGR_CSSETUP_Msk)
#define SPI_CSCFGR_HOLD(x)     (((uint32_t)(((uint32_t)(x)) << SPI_CSCFGR_CSHOLD_Pos)) & SPI_CSCFGR_CSHOLD_Msk)
#define SPI_CSCFGR_IDLE(x)     (((uint32_t)(((uint32_t)(x)) << SPI_CSCFGR_CSIDLE_Pos)) & SPI_CSCFGR_CSIDLE_Msk)

/* Control Register Bit Fields */
#define SPI_CR_CONTEN(x)       (((uint32_t)(((uint32_t)(x)) << SPI_CR_CONTEN_Pos)) & SPI_CR_CONTEN_Msk)
#define SPI_CR_CSLOOSE(x)      (((uint32_t)(((uint32_t)(x)) << SPI_CR_CSLOOSE_Pos)) & SPI_CR_CSLOOSE_Msk)
#define SPI_CR_SPLDLY(x)       (((uint32_t)(((uint32_t)(x)) << SPI_CR_SPLDLY_Pos)) & SPI_CR_SPLDLY_Msk)
#define SPI_CR_SCKL(x)         (((uint32_t)(((uint32_t)(x)) << SPI_CR_SCKL_Pos)) & SPI_CR_SCKL_Msk)
#define SPI_CR_SCKH(x)         (((uint32_t)(((uint32_t)(x)) << SPI_CR_SCKH_Pos)) & SPI_CR_SCKH_Msk)

/* Interrupt Enable Register Bit Fields */
#define SPI_IER_TNFIE(x)       (((uint32_t)(((uint32_t)(x)) << SPI_IER_TNFIE_Pos)) & SPI_IER_TNFIE_Msk)
#define SPI_IER_TUIE(x)        (((uint32_t)(((uint32_t)(x)) << SPI_IER_TUIE_Pos)) & SPI_IER_TUIE_Msk)
#define SPI_IER_RNEIE(x)       (((uint32_t)(((uint32_t)(x)) << SPI_IER_RNEIE_Pos)) & SPI_IER_RNEIE_Msk)
#define SPI_IER_ROIE(x)        (((uint32_t)(((uint32_t)(x)) << SPI_IER_ROIE_Pos)) & SPI_IER_ROIE_Msk)

/* Status Register Bit Fields */
#define SPI_SR_TUFF(x)         (((uint32_t)(((uint32_t)(x)) << SPI_SR_TUFF_Pos)) & SPI_SR_TUFF_Msk)
#define SPI_SR_ROFF(x)         (((uint32_t)(((uint32_t)(x)) << SPI_SR_ROFF_Pos)) & SPI_SR_ROFF_Msk)

/*!
 * @brief SPI status flags
 */
typedef enum {
    SPI_STATUS_TX_NOT_FULL  = SPI_SR_TNFF_Msk, /*!< Tx fifo not full flag */
    SPI_STATUS_TX_UNDERFLOW = SPI_SR_TUFF_Msk, /*!< Tx fifo underflow flag */
    SPI_STATUS_RX_NOT_EMPTY = SPI_SR_RNEF_Msk, /*!< Rx fifo not empty flag */
    SPI_STATUS_RX_OVERFLOW  = SPI_SR_ROFF_Msk, /*!< Rx fifo overflow flag */
    SPI_STATUS_MODULE_BUSY  = SPI_SR_MBF_Msk   /*!< Module busy flag */
} spi_status_flag_t;

/*!
 * @brief SPI interrupt events
 */
typedef enum {
    SPI_INT_TX_NOT_FULL     = SPI_IER_TNFIE_Msk, /*!< Tx fifo not full */
    SPI_INT_TX_UNDERFLOW    = SPI_IER_TUIE_Msk,  /*!< Tx fifo underflow */
    SPI_INT_RX_NOT_EMPTY    = SPI_IER_RNEIE_Msk, /*!< Rx fifo not empty */
    SPI_INT_RX_OVERFLOW     = SPI_IER_ROIE_Msk   /*!< Rx fifo overflow */
} spi_interrupt_t;

/*******APIs*******************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif

/*!
 * @brief Enable SPI instance
 *
 * @param[in] regBase: SPI register base address
 * @return None
 */
static inline void SPI_REG_Enable(SPI_Type* regBase)
{
    uint32_t regValue = regBase->CFGR;

    regValue &= (~SPI_CFGR_SPIEN_Msk);
    regValue |= SPI_CFGR_SPIEN(1U);
    regBase->CFGR = regValue;
}

/*!
 * @brief Disable SPI instance
 *
 * @param[in] regBase: SPI register base address
 * @return ERR_SUCCESS: Disable success
 *         ERR_BUSY: Current spi instance is busy, cannot be disabled
 */
errcode_t SPI_REG_Disable(SPI_Type* regBase);

/*!
 * @brief Set SPI insance as master or slave
 *
 * @param[in] regBase: SPI register base address
 * @param[in] mode: SPI_MODE_MASTER: Master mode
 *                  SPI_MODE_SLAVE: Slave mode
 * @return None
 */
static inline void SPI_REG_SetMasterSlaveMode(SPI_Type* regBase, spi_mode_t mode)
{
    uint32_t regValue = regBase->CFGR;

    regValue &= (~SPI_CFGR_MASTER_Msk);
    regValue |= SPI_CFGR_MASTER((mode == SPI_MODE_MASTER) ? 1U : 0U);
    regBase->CFGR = regValue;
}

/*!
 * @brief Check if this SPI instance is master mode
 *
 * @param[in] regBase: SPI register base address
 * @return true: Master mode
 *         false: Slave mode
 */
static inline bool SPI_REG_IsMaster(SPI_Type* regBase)
{
    uint32_t regValue = regBase->CFGR;

    regValue = (regValue & SPI_CFGR_MASTER_Msk) >> SPI_CFGR_MASTER_Pos;

    return (regValue == 1U) ? true : false;
}

/*!
 * @brief Set SPI's pin configuration
 *
 * @param[in] regBase: SPI register base address
 * @param[in] pinConfig: Refer to spi_pin_config_t
 * @return None
 */
static inline void SPI_REG_SetPinConfig(SPI_Type* regBase, spi_pin_config_t pinConfig)
{
    uint32_t regValue = regBase->CFGR;

    regValue &= (~SPI_CFGR_PINCFG_Msk);
    regValue |= SPI_CFGR_PINCFG((pinConfig == SPI_PIN_SOUT_MISO_SIN_MOSI) ? 0U : 1U);
    regBase->CFGR = regValue;
}

/*!
 * @brief Set CS polarity
 *
 * @param[in] regBase: SPI register base address
 * @param[in] csPol: CS polarity
 * @return None
 */
static inline void SPI_REG_SetCsPolarity(SPI_Type* regBase, spi_cs_pol_t csPol)
{
    uint32_t regValue = regBase->CFGR;

    regValue &= (~SPI_CFGR_CSPOL_Msk);
    regValue |= SPI_CFGR_CSPOL((csPol == SPI_CS_POL_LOW) ? 0U : 1U);
    regBase->CFGR = regValue;
}

/*!
 * @brief Set Clock polarity
 *
 * @param[in] regBase: SPI register base address
 * @param[in] clkPol: Clock polarity
 * @return None
 */
static inline void SPI_REG_SetClockPolarity(SPI_Type* regBase, spi_clk_pol_t clkPol)
{
    uint32_t regValue = regBase->CFGR;

    regValue &= (~SPI_CFGR_CPOL_Msk);
    regValue |= SPI_CFGR_CPOL((clkPol == SPI_CLK_POL_LOW) ? 0U : 1U);
    regBase->CFGR = regValue;
}

/*!
 * @brief Set Clock phase
 *
 * @param[in] regBase: SPI register base address
 * @param[in] clkPha: Clock phase
 * @return None
 */
static inline void SPI_REG_SetClockPhase(SPI_Type* regBase, spi_clk_pha_t clkPha)
{
    uint32_t regValue = regBase->CFGR;

    regValue &= (~SPI_CFGR_CPHA_Msk);
    regValue |= SPI_CFGR_CPHA((clkPha == SPI_CLK_PHA_1ST) ? 0U : 1U);
    regBase->CFGR = regValue;
}

/*!
 * @brief Enbale transmit with dma
 *
 * @param[in] regBase: SPI register base address
 * @param[in] enable: true: Enable
 *                    false: Disable
 * @return None
 */
static inline void SPI_REG_SetTxDmaEnable(SPI_Type* regBase, bool enable)
{
    uint32_t regValue = regBase->CFGR;

    regValue &= (~SPI_CFGR_TDMAEN_Msk);
    regValue |= SPI_CFGR_TDMAEN(enable ? 1U : 0U);
    regBase->CFGR = regValue;
}

/*!
 * @brief Enbale receive with dma
 *
 * @param[in] regBase: SPI register base address
 * @param[in] enable: true: Enable
 *                    false: Disable
 * @return None
 */
static inline void SPI_REG_SetRxDmaEnable(SPI_Type* regBase, bool enable)
{
    uint32_t regValue = regBase->CFGR;

    regValue &= (~SPI_CFGR_RDMAEN_Msk);
    regValue |= SPI_CFGR_RDMAEN(enable ? 1U : 0U);
    regBase->CFGR = regValue;
}

/*!
 * @brief Set frame size
 *
 * @param[in] regBase: SPI register base address
 * @param[in] frameSize: SPI frame size, 8bit、16bit、32bit
 * @return None
 */
static inline void SPI_REG_SetFrameSize(SPI_Type* regBase, spi_frame_size_t frameSize)
{
    uint32_t regValue = regBase->CFGR;

    regValue &= (~SPI_CFGR_FRAMESZ_Msk);
    regValue |= SPI_CFGR_FRAMESZ(frameSize);
    regBase->CFGR = regValue;
}

/*!
 * @brief Set transmit order, MSB or LSB
 *
 * @param[in] regBase: SPI register base address
 * @param[in] txOrder: Transmit order
 * @return None
 */
static inline void SPI_REG_SetTransmitOrder(SPI_Type* regBase, spi_transfer_order_t txOrder)
{
    uint32_t regValue = regBase->CFGR;

    regValue &= (~SPI_CFGR_TMSBF_Msk);
    regValue |= SPI_CFGR_TMSBF((txOrder == SPI_TRANSFER_ORDER_MSB) ? 1U : 0U);
    regBase->CFGR = regValue;
}

/*!
 * @brief Set receive order, MSB or LSB
 *
 * @param[in] regBase: SPI register base address
 * @param[in] rxOrder: Receive order
 * @return None
 */
static inline void SPI_REG_SetReceiveOrder(SPI_Type* regBase, spi_transfer_order_t rxOrder)
{
    uint32_t regValue = regBase->CFGR;

    regValue &= (~SPI_CFGR_RMSBF_Msk);
    regValue |= SPI_CFGR_RMSBF((rxOrder == SPI_TRANSFER_ORDER_MSB) ? 1U : 0U);
    regBase->CFGR = regValue;
}

/*!
 * @brief Set continuous mode
 *
 * @param[in] regBase: SPI register base address
 * @param[in] contEnable: true: Enable
 *                        false: Disable
 * @return None
 */
static inline void SPI_REG_SetContinuousMode(SPI_Type* regBase, bool contEnable)
{
    uint32_t regValue = regBase->CR;

    regValue &= (~SPI_CR_CONTEN_Msk);
    regValue |= SPI_CR_CONTEN((contEnable) ? 1U : 0U);
    regBase->CR = regValue;
}

/*!
 * @brief Release or loose CS pin, only used in continuous mode in master mode
 *
 * @param[in] regBase: SPI register base address
 * @return None
 */
static inline void SPI_REG_ReleaseCS(SPI_Type* regBase)
{
    uint32_t regValue = regBase->CR;

    regValue &= (~SPI_CR_CSLOOSE_Msk);
    regValue |= SPI_CR_CSLOOSE(1U);
    regBase->CR = regValue;
}

/*!
 * @brief Set sample delay param in master mode
 *
 * @param[in] regBase: SPI register base address
 * @param[in] sampleDelay: Sample delay configurations
 * @return None
 */
static inline void SPI_REG_SetSampleDelay(SPI_Type* regBase, spi_sample_delay_t sampleDelay)
{
    uint32_t regValue = regBase->CR;

    regValue &= (~SPI_CR_SPLDLY_Msk);
    regValue |= SPI_CR_SPLDLY(sampleDelay);
    regBase->CR = regValue;
}

/*!
 * @brief Set SCK low time, used in baudrate configuration
 *
 * @param[in] regBase: SPI register base address
 * @param[in] sckLow: SCK low time
 * @return None
 */
static inline void SPI_REG_SetSckLowTime(SPI_Type* regBase, uint8_t sckLow)
{
    uint32_t regValue = regBase->CR;

    regValue &= (~SPI_CR_SCKL_Msk);
    regValue |= SPI_CR_SCKL(sckLow);
    regBase->CR = regValue;
}

/*!
 * @brief Set SCK High time, used in baudrate configuration
 *
 * @param[in] regBase: SPI register base address
 * @param[in] sckHigh: SCK high time
 * @return None
 */
static inline void SPI_REG_SetSckHighTime(SPI_Type* regBase, uint8_t sckHigh)
{
    uint32_t regValue = regBase->CR;

    regValue &= (~SPI_CR_SCKH_Msk);
    regValue |= SPI_CR_SCKH(sckHigh);
    regBase->CR = regValue;
}

/*!
 * @brief Set CS setup time, used in transfer timing configuration
 *
 * @param[in] regBase: SPI register base address
 * @param[in] csSetup: CS setup time
 * @return None
 */
static inline void SPI_REG_SetCsSetupTime(SPI_Type* regBase, uint8_t csSetup)
{
    uint32_t regValue = regBase->CSCFGR;

    regValue &= (~SPI_CSCFGR_CSSETUP_Msk);
    regValue |= SPI_CSCFGR_SETUP(csSetup);
    regBase->CSCFGR = regValue;
}

/*!
 * @brief Set CS hold time, used in transfer timing configuration
 *
 * @param[in] regBase: SPI register base address
 * @param[in] csHold: CS hold time
 * @return None
 */
static inline void SPI_REG_SetCsHoldTime(SPI_Type* regBase, uint8_t csHold)
{
    uint32_t regValue = regBase->CSCFGR;

    regValue &= (~SPI_CSCFGR_CSHOLD_Msk);
    regValue |= SPI_CSCFGR_HOLD(csHold);
    regBase->CSCFGR = regValue;
}

/*!
 * @brief Set CS idle time, used in transfer timing configuration
 *
 * @param[in] regBase: SPI register base address
 * @param[in] csIdle: CS idle time
 * @return None
 */
static inline void SPI_REG_SetCsIdleTime(SPI_Type* regBase, uint8_t csIdle)
{
    uint32_t regValue = regBase->CSCFGR;

    regValue &= (~SPI_CSCFGR_CSIDLE_Msk);
    regValue |= SPI_CSCFGR_IDLE(csIdle);
    regBase->CSCFGR = regValue;
}

/*!
 * @brief Get status flags
 *
 * @param[in] regBase: SPI register base address
 * @param[in] statusFlag: Status flags
 * @return None
 */
static inline bool SPI_REG_GetStatusFlag(SPI_Type* regBase, spi_status_flag_t statusFlag)
{
    return ((regBase->SR & (uint32_t)statusFlag) == 0U) ? false : true;
}

/*!
 * @brief Clear status flags
 *
 * @param[in] regBase: SPI register base address
 * @param[in] statusFlag: Status flags
 * @return None
 */
static inline void SPI_REG_ClearStatusFlag(SPI_Type* regBase, spi_status_flag_t statusFlag)
{
    regBase->SR = (uint32_t)statusFlag;
}

/*!
 * @brief Clear error status flags
 *
 * @param[in] regBase: SPI register base address
 * @param[in] statusFlag: Status flags
 * @return None
 */
static inline void SPI_REG_ClearErrorStatusFlag(SPI_Type* regBase, uint32_t statusFlag)
{
    regBase->SR = statusFlag;
}

/*!
 * @brief Set interrupt enable
 *
 * @param[in] regBase: SPI register base address
 * @param[in] intSource: Interrupt source
 * @param[in] enable: true: Enable
 *                    false: Disable
 * @return None
 */
static inline void SPI_REG_SetIntEnable(SPI_Type* regBase, spi_interrupt_t intSource, bool enable)
{
    if (enable) {
        regBase->IER |= (uint32_t)intSource;
    } else {
        regBase->IER &= (~(uint32_t)intSource);
    }
}

/*!
 * @brief Set error interrupt enable
 *
 * @param[in] regBase: SPI register base address
 * @param[in] intSource: Interrupt source
 * @param[in] enable: true: Enable
 *                    false: Disable
 * @return None
 */
static inline void SPI_REG_SetErrorIntEnable(SPI_Type* regBase, uint32_t intSource, bool enable)
{
    if (enable) {
        regBase->IER |= intSource;
    } else {
        regBase->IER &= (~intSource);
    }
}
/*!
 * @brief Write data to data register
 *
 * @param[in] regBase: SPI register base address
 * @param[in] data: Data to write to data register
 * @return None
 */
static inline void SPI_REG_WriteData(SPI_Type* regBase, uint32_t data)
{
    regBase->DR = (uint32_t)data;
}

/*!
 * @brief Read data from data register
 *
 * @param[in] regBase: SPI register base address
 * @return Data read from data register
 */
static inline uint32_t SPI_REG_ReadData(SPI_Type* regBase)
{
    return (uint32_t)(regBase->DR);
}

/*!
 * @brief Get address of data register, used in dma transfer
 *
 * @param[in] regBase: SPI register base address
 * @return Address of data register
 */
static inline uint32_t SPI_REG_GetDataAddress(SPI_Type* regBase)
{
    return (uint32_t)(&(regBase->DR));
}

#if defined(__cplusplus)
}
#endif

#endif /* SPI_REG_ACCESS_H */

/*******EOF********************************************************************/


